K4X56163PE Datasheet, PDF (18/48 Pages) Samsung semiconductor – 16M x16 Mobile DDR SDRAM

K4X56163PE-L(F)G
Mobile-DDR SDRAM
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where
tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the
earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which
does not interrupt the burst.
5. Refer to "3.3.2 Burst write operation"
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst
stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has
been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a
high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is
not supported during a write burst operation.
< Burst Length=4, CAS Latency= 3 >
0
1
2
3
CK, CK
Command READ A Burst Stop
NOP
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
DQS
CAS Latency=3
DQs
The burst read ends after a delay equal to the CAS latency.
Dout 0 Dout 1
Figure.12 Burst stop timing
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L_BST (“BST Latency”) clock cycles before the clock
edge at which the output buffers are tristated, where L_BST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
18
March 2004