K4X56163PE Datasheet, PDF (13/48 Pages) Samsung semiconductor – 16M x16 Mobile DDR SDRAM

K4X56163PE-L(F)G
Mobile-DDR SDRAM
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The
address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The
first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS
from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subse-
quent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data
supplied to the DQ pins will be ignored.
< Burst Length=4 >
0
1 *1
2
3
4
5
6
CK
CK
Command NOP
WRITEA
NOP
WRITEB
NOP
NOP
NOP
DQS
DQs
tDQSSmax
t_WPRES*1
*1
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
7
NOP
8
NOP
Figure.6 Burst write operation timing
1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
13
March 2004