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K4B1G0446D Datasheet, PDF (59/60 Pages) Samsung semiconductor – 1Gb D-die DDR3 SDRAM Specification
K4B1G04(08/16)46D
1Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
CK
tIS tIH
CK
DQS
DQS
VDDQ
tDS tDH
nominal
line
VIH(AC) min
VIH(DC) min
VREF to ac
region
VREF(DC)
tangent
line
tDS tDH
tVAC
tangent
line
VIL(DC) max
VIL(AC) max
nominal
line
VSS
Delta TF
VREF to ac
region
Delta TR
SeRtiuspinSgleSwignRaalt=e
tangent
line[VIH(AC)min
Delta TR
-
VREF(DC)]
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
Falling Signal =
Delta TF
Figure 27 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
Page 59 of 60
Rev. 1.1 August 2008