K4B1G0446D Datasheet, PDF (25/60 Pages) Samsung semiconductor – 1Gb D-die DDR3 SDRAM Specification

K4B1G04(08/16)46D
1Gb DDR3 SDRAM
Note :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage
changes after calibration, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that V_DDQ = V_DD and that V_SSQ = V_SS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV_DDQ. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.2XV_DDQ and 0.8XV_DDQ.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply V_IH(AC) to pin under test and measure current I(V_IH(AC)), then apply V_IL(AC) to pin under test and measure current I(V_IL(AC)) perspectively
RTT =
V_IH(AC) - V_IL(AC)
I(V_IH(AC)) - I(V_IL(AC))
6. Measurement definition for V_M and ∆V_M : Measure voltage (V_M) at test pin (midpoint) with no load
∆ V_M =
2 x V_{M - 1 x 100}
V_DDQ
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
∆T = T - T(@calibration); ∆V = V_DDQ - V_DDQ (@calibration); V_DD = V_DDQ
[ Table 26 ] ODT Sensitivity Definition
Min
RTT
0.9 - dR_TTdT * |∆T| - dR_TTdV * |∆V|
Max
1.6 + dR_TTdT * |∆T| + dR_TTdV * |∆V|
[ Table 27 ] ODT Voltage and Temperature Sensitivity
Min
Max
dR_TTdT
0
1.5
dR_TTdV
0
0.15
These parameters may not be subject to production test. They are verified by design and characterization.
Units
RZQ/2,4,6,8,12
Units
%/°C
%/mV
Page 25 of 60
Rev. 1.1 August 2008