K4B1G0446D Datasheet, PDF (26/60 Pages) Samsung semiconductor – 1Gb D-die DDR3 SDRAM Specification

K4B1G04(08/16)46D
9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.
1Gb DDR3 SDRAM
CK,CK
V_DDQ
DUT
DQ, DM
DQS , DQS
TDQS , TDQS
V_SSQ
Timing Reference Points
RTT
V_TT=
V_SSQ
=25 ohm
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definition
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided
in Table 29.
[ Table 28 ] ODT Timing Definitions
Symbol
Begin Point Definition
tAON
Rising edge of CK - CK defined by the end point of ODTLon
tAONPD Rising edge of CK - CK with ODT being first registered high
tAOF
Rising edge of CK - CK defined by the end point of ODTLoff
tAOFPD Rising edge of CK - CK with ODT being first registered low
tADC
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4 of ODTLcwn8
End Point Definition
Extrapolated point at V_SSQ
Extrapolated point at V_SSQ
End point: Extrapolated point at V_{RTT_Nom}
End point: Extrapolated point at V_{RTT_Nom}
End point: Extrapolated point at V_{RTT_Wr} and V_{RTT_Nom}
respectively
Figute
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
[ Table 29 ] Reference Settings for ODT Timing Measurements
Measured
Parameter
RTT_Nom Setting
RTT_Wr Setting
tAON
tAONPD
tAOF
tAOFPD
tADC
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/4
R_ZQ/12
R_ZQ/12
NA
NA
NA
NA
NA
NA
NA
NA
R_ZQ/2
V_SW1[V]
0.05
0.10
0.05
0.10
0.05
0.10
0.05
0.10
0.20
V_SW2[V]
0.10
0.20
0.10
0.20
0.10
0.20
0.10
0.20
0.30
Note
Page 26 of 60
Rev. 1.1 August 2008