K4B1G0446D Datasheet, PDF (40/60 Pages) Samsung semiconductor – 1Gb D-die DDR3 SDRAM Specification

K4B1G04(08/16)46D
1Gb DDR3 SDRAM
12.0 Input/Output Capacitance
[ Table 41 ] Input / Output Capacitance
Parameter
Symbol
Input/output capacitance
CIO
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
CCK
Input capacitance delta
(CK and CK)
CDCK
Input capacitance
CI
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
CDDQS
Input capacitance delta
(All control input-only pins)
CDI_CTRL
Input capacitance delta
(all ADD and CMD input-onlypins)
CDI_ADD_CMD
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO
Input/output capacitance of ZQ pin
CZQ
DDR3-800
Min Max
1.5
3.0
0.8
1.6
0
0.15
0.75
1.5
0
0.2
-0.5
0.3
-0.5
0.5
-0.5
0.3
-
3
DDR3-1066
Min Max
1.5
2.7
0.8
1.6
0
0.15
0.75
1.5
0
0.2
-0.5
0.3
-0.5
0.5
-0.5
0.3
-
3
DDR3-1333
Min Max
1.5
2.5
0.8
1.4
0
0.15
0.75
1.3
0
0.15
-0.4
0.2
-0.4
0.4
-0.5
0.3
-
3
DDR3-1600
Units Notes
Min Max
1.5
2.3 pF 1,2,3
0.8
1.4 pF 2,3
0
0.15 pF 2,3,4
0.75
1.3 pF 2,3,6
0
0.15 pF 2,3,5
-0.4
0.2 pF 2,3,7,8
-0.4
0.4 pF 2,3,9,10
-0.5
0.3 pF 2,3,11
-
3
pF 2, 3, 12
Note :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER( VNA)") with V_DD, V_DDQ, V_SS, V_SSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary).
V_DD=V_DDQ=1.5V, V_BIAS=V_DD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Page 40 of 60
Rev. 1.1 August 2008