RL78G12_15 Datasheet, PDF (94/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)
3.5.2 Serial interface IICA
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) mode
Unit
Standard Mode
Fast Mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency
fSCL
Fast mode: fCLK ≥ 3.5 MHz
0
400
kHz
Normal mode: fCLK ≥ 1 MHz
0
100
kHz
Setup time of restart condition
tSU:STA
4.7
0.6
μs
Hold time^{Note 1}
tHD:STA
4.0
0.6
μs
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
μs
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
μs
Data setup time (reception)
tSU:DAT
250
100
ns
Data hold time (transmission)^{Note 2} tHD:DAT
0
3.45
0
0.9
μs
Setup time of stop condition
tSU:STO
4.0
0.6
μs
Bus-free time
tBUF
4.7
1.3
μs
Notes 1.
2.
The first clock pulse is generated after this period when the start/restart condition is detected.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the
peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1,
VOL1) must satisfy the values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Normal mode:
Fast mode:
Cb = 400 pF, Rb = 2.7 kΩ
Cb = 320 pF, Rb = 1.1 kΩ
tLOW tR
IICA serial transfer timing
SCLA0
tHD:DAT
tHD:STA
tHIGH tF
tSU:DAT
tSU:STA
tHD:STA
tSU:STO
SDAA0
t BUF
Stop
Start
condition condition
Restart
condition
Stop
condition
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 94 of 106