RL78G12_15 Datasheet, PDF (89/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Unit
Mode
MIN.
MAX.
SCKp cycle time ^{Note 1}
tKCY2
4.0 V ≤ VDD ≤ 5.5 V,
20 MHz < fMCK ≤ 24 MHz
24/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
20/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.7 V ≤ VDD < 4.0 V,
20 MHz < fMCK ≤ 24 MHz
32/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
28/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
24/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK
ns
fMCK ≤ 4 MHz
12/fMCK
ns
2.4 V ≤ VDD < 3.3 V,
20 MHz < fMCK ≤ 24 MHz
72/fMCK
ns
1.6 V ≤ Vb ≤ 2.0 V
16 MHz < fMCK ≤ 20 MHz
64/fMCK
ns
8 MHz < fMCK ≤ 16 MHz
52/fMCK
ns
4 MHz < fMCK ≤ 8 MHz
32/fMCK
ns
fMCK ≤ 4 MHz
20/fMCK
ns
SCKp high-/low-level
tKH2,
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
width
tKL2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
tKCY2/2 − 24
ns
tKCY2/2 − 36
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
tKCY2/2 − 100
ns
SIp setup time
(to SCKp↑) ^{Note 2}
tSIK2
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1/fMCK + 40
ns
1/fMCK + 40
ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V
1/fMCK + 60
ns
SIp hold time
tKSI2
(from SCKp↑) ^{Note 3}
1/fMCK + 62
ns
Delay time from SCKp↓ to tKSO2
SOp output ^{Note 4}
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
ns
240
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
ns
428
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
ns
1146
Notes 1.
2.
3.
4.
Transfer rate in the SNOOZE mode: MAX. 1 Mbps
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions
1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output
mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer
selected.
2. CSI01 and CSI11 cannot communicate at different potential.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 89 of 106