RL78G12_15 Datasheet, PDF (31/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)
2.5 Peripheral Functions Characteristics
<R> AC Timing Test Point
VIH/VOH
VIL/VOL
Test points
VIH/VOH
VIL/VOL
2.5.1 Serial array unit
<R> (1) During communication at same potential (UART mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol
Conditions
HS (high-speed
LS (low-speed
Unit
main) Mode
main) Mode
MIN.
MAX.
MIN.
MAX.
Transfer rate
Note 1
Theoretical value of the maximum transfer rate
fCLK = fMCK^Note2
fMCK/6
4.0
fMCK/6
1.3
bps
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
<R>
2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
RL78
microcontroller
RxDq
Rx
User's device
Tx
TxDq
RxDq
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
Remarks 1.
2.
q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial
mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 31 of 106