RL78G12_15 Datasheet, PDF (81/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)
(4) During communication at same potential (simplified I²C mode)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
MAX.
SCLr clock frequency
fSCL
Cb = 100 pF, Rb = 3 kΩ
100 ^{Note 1}
kHz
Hold time when SCLr = “L”
tLOW
Cb = 100 pF, Rb = 3 kΩ
4600
ns
Hold time when SCLr = “H”
tHIGH
Cb = 100 pF, Rb = 3 kΩ
4600
ns
Data setup time (reception)
tSU:DAT
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 580 ^{Note 2}
ns
Data hold time (transmission)
tHD:DAT
Cb = 100 pF, Rb = 3 kΩ
0
1420
ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
Simplified I²C mode connection diagram (during communication at same potential)
SDAr
RL78
microcontroller
VDD
Rb
SDA
User's device
SCLr
SCL
SCLr
Simplified I²C mode serial transfer timing (during communication at same potential)
tLOW
1/fSCL
tHIGH
SDAr
tHD:DAT
tSU:DAT
Remarks 1.
2.
3.
Rb [Ω]:Communication line (SDAr) pull-up resistance
Cb [F]: Communication line (SCLr, SDAr) load capacitance
r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn).
m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 81 of 106