RL78G12_15 Datasheet, PDF (43/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)
<R> (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) LS (low-speed main) Unit
Mode
Mode
MIN.
MAX.
MIN.
MAX.
SCKp cycle time
tKCY1
tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
300
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
1150
ns
2.7 V ≤ VDD < 4.0 V,
500
1150
ns
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V ^Note,
1150
1150
ns
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 −75
tKCY1/2−75
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
tKCY1/2 −170
tKCY1/2−170
ns
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V ^Note,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −458
tKCY1/2−458
ns
SCKp low-level width tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 −12
tKCY1/2−50
ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
tKCY1/2 −18
tKCY1/2−50
ns
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V ^Note,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −50
tKCY1/2−50
ns
Note Use it with VDD ≥ Vb.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 43 of 106