RL78G12_15 Datasheet, PDF (83/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
3. ELECTRICAL SPECIFICATIONS (G: TA = −40 to +105°C)
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
Maximum transfer rate =
1
{−Cb × Rb × ln (1 −
2.0
Vb
)} × 3
[bps]
Baud rate error (theoretical value) =
1
Transfer rate × 2
− {−Cb × Rb × ln (1 −
2.0
Vb
)}
(
1
Transfer
rate
)
×
Number
of
transferred
bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
7. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
Maximum transfer rate =
1
{−Cb × Rb × ln (1 −
1.5
Vb
)} × 3
[bps]
Baud rate error (theoretical value) =
1
Transfer rate × 2
− {−Cb × Rb × ln (1 −
1.5
Vb
)}
(
1
Transfer
rate
)
×
Number
of
transferred
bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
8. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).
For VIH and VIL, see the DC characteristics with TTL input buffer selected.
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 83 of 106