RL78G12_15 Datasheet, PDF (36/110 Pages) Renesas Technology Corp – RENESAS MCU

RL78/G12
2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)
Remarks 1.
2.
p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
only for the R5F102 products.)
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode
register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the
R5F102 products.))
<R> (5) During communication at same potential (simplified I²C mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
LS (low-speed main) Mode
MIN.
MAX.
SCLr clock frequency
fSCL
1.8 V ≤ VDD ≤ 5.5 V,
400 ^{Note 1}
kHz
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
300 ^{Note 1}
kHz
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “L”
tLOW
1.8 V ≤ VDD ≤ 5.5 V,
1150
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
1550
ns
Cb = 100 pF, Rb = 5 kΩ
Hold time when SCLr = “H”
tHIGH
1.8 V ≤ VDD ≤ 5.5 V,
1150
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
1550
ns
Cb = 100 pF, Rb = 5 kΩ
Data setup time (reception)
tSU:DAT
1.8 V ≤ VDD ≤ 5.5 V,
1/fMCK + 145 ^Note
ns
2
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
1/fMCK + 230 ^Note
ns
2
Cb = 100 pF, Rb = 5 kΩ
Data hold time (transmission)
tHD:DAT
1.8 V ≤ VDD ≤ 5.5 V,
0
355
ns
Cb = 100 pF, Rb = 3 kΩ
1.8 V ≤ VDD < 2.7 V,
0
405
ns
Cb = 100 pF, Rb = 5 kΩ
Notes 1. The value must also be equal to or less than fMCK/4.
<R>
2. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
(Remarks are listed on the next page.)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 36 of 106