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| HD6413003TF10 Datasheet, PDF (565/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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T1
ø
tAD
T2
T3
A23 to A0
AS
CS3
RD (read)
D15 to D0
(read)
HWR, LWR
(write)
D15 to D0
(write)
tRAD1
tAS1
tRSD
tWSD
tWDS2
tRAD3
tRP
tSD
tRDS
tRDH*
tSD
RFSH
Note: * Stipulation from earliest CS3 and RD negate timing.
Figure 18-13 PSRAM Bus Timing (Read/Write): Three-State Access
ø
A23 to A0
AS
CS3, HWR,
LWR, RD
RFSH
T1
T2
tRAD2
T3
tRAD3
Figure 18-14 PSRAM Bus Timing (Refresh Cycle): Three-State Access
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