HD6413003TF10 Datasheet, PDF (153/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

DDR Write Timing: Data written to a data direction register (DDR) to change a CS_n pin from
CS_n output to generic input, or vice versa, takes effect starting from the T₃ state of the DDR write
cycle. Figure 6-21 shows the timing when the CS₁ pin is changed from generic input to CS₁
output.
ø
Address
CS₁
T₁
T₂
T₃
P8DDR address
High impedance
Figure 6-21 DDR Write Timing
6.4.3 BREQ Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes low, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
If BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
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