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| HD6413003TF10 Datasheet, PDF (240/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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DREQ
CPU cycle
DMAC cycle
CPU cycle
T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T 1
A 23 to A0
RD
HWR , LWR
Minimum 4 states
Next sampling point
Figure 8-17 Timing of DMAC Activation by Low DREQ Level in Normal Mode
Figure 8-18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
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