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HD6413003TF10 Datasheet, PDF (554/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
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Table 18-7 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
DMAC DREQ setup
time
tDRQS
DREQ hold
time
tDRQH
TEND delay
time 1
tTED1
TEND delay
time 2
tTED2
ITU Timer output
delay time
tTOCD
Timer input
setup time
tTICS
Timer clock
tTCKS
input setup time
Timer
clock
pulse
width
Single
edge
Both
edges
tTCKWH
tTCKWL
SCI Input Asyn-
tSCYC
clock chronous
cycle
Syn-
tSCYC
chronous
Input clock rise tSCKR
time
Input clock fall
time
tSCKR
Input clock
pulse width
tSCKW
Condition A Condition B Condition C
8 MHz
10 MHz
16 MHz
Min Max Min Max Min Max
40 — 30 — 30 —
10 — 10 — 10 —
— 100 — 50 — 50
— 100 — 50 — 50
— 100 — 100 — 100
50 — 50 — 50 —
50 — 50 — 50 —
1.5 — 1.5 — 1.5 —
2.5 — 2.5 — 2.5 —
4
—4
—4
—
6
—6
—6
—
— 1.5 — 1.5 — 1.5
— 1.5 — 1.5 — 1.5
0.4 0.6 0.4 0.6 0.4 0.6
Unit
ns
ns
tCYC
tSCYC
Test
Conditions
Figure 18-27
Figure 18-25,
Figure 18-26
Figure 18-21
Figure 18-22
Figure 18-23
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