HD6413003TF10 Datasheet, PDF (530/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16.3 System Clock Divider (Clock-Halving Version)
The system clock divider divides the oscillator output by 2 to generate the system clock (ø).
16.4 Duty Adjustment Circuit (1:1 Version)
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate a system clock (ø).
16.5 Prescalers
The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).
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