HD6413003TF10 Datasheet, PDF (533/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
(Initial value)
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 8 ms. See table 17-3. If an external
clock is used, any setting is permitted.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0
0
0
Waiting time = 8192 states
1
Waiting time = 16384 states
1
0
Waiting time = 32768 states
1
Waiting time = 65536 states
1
0
—
Waiting time = 131072 states
1
—
Waiting time = 4 states*
Note: * Do not use this setting for the 1:1 clock version.
(Initial value)
513