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HD6413003TF10 Datasheet, PDF (518/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Table 14-4 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min
Typ
Max
Synchronization delay
tD
10
â
17
Input sampling time
tSPL
â
80
â
A/D conversion time
tCONV
259
â
266
Note: Values in the table are numbers of states.
CKS = 1
Min
Typ
Max
6
â
9
â
40
â
131
â
134
14.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 14-6 shows the
timing.
ø
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 14-6 External Trigger Input Timing
498
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