HD6413003TF10 Datasheet, PDF (394/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T₃ state of a write cycle, input
capture takes priority and the write to the buffer register is not performed.
See figure 10-69.
Buffer register write cycle
T₁
T₂
T₃
ø
Address
BR address
Internal write signal
Input capture signal
GR
N
BR
M
X
TCNT value
N
Figure 10-69 Contention between Buffer Register Write and Input Capture
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