HD6413003TF10 Datasheet, PDF (529/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

External Clock
• Clock-halving version
The external clock signal should have a frequency equal to twice the system clock frequency
(ø) and a duty cycle of 40% to 60%.
• 1:1 version
The external clock frequency should be equal to the system clock frequency (ø). Table 16-3
and figure 16-6 indicate the clock timing.
Table 16-3 Clock Timing
Item
External clock rise
time
External clock fall
time
External clock
input duty (a/tcyc)
ø clock width
duty (b/tcyc)
V_CC = 2.7 to 5.5 V V_CC = 5.0 V ± 10%
Symbol Min Max
Min
Max
Unit Test Conditions
t_EXr
—
10
—
5
ns
t_EXf
—
10
—
5
ns
—
30
70
40
60
—
40
60
30
70
40
60
40
60
% ø ≥ 5 MHz Figure
% ø < 5 MHz ^16-6
%
t_cyc
a
EXTAL
V_CC × 0.5
t_EXr
t_EXf
t _cyc
b
Ø
V_CC × 0.5
Figure 16-6 External Clock Input Timing
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