HD6413003TF10 Datasheet, PDF (531/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 Power-Down State
17.1 Overview
The H8/3003 has a power-down state that greatly reduces power consumption by halting CPU
functions. The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
Table 17-1 indicates the methods of entering and exiting these power-down modes and the status
of the CPU and on-chip supporting modules in each mode.
Table 17-1 Power-Down State
State
Mode
Entering
Conditions
CPU
Refresh Supporting
I/O
Clock CPU Registers DMAC Controller Functions RAM Ports
Exiting
Conditions
Sleep
mode
SLEEP instruc- Active
tion executed
while SSBY = 0
in SYSCR
Halted Held
Active Active
Active
Held Held
• Interrupt
• RES
• STBY
Software
standby
mode
SLEEP instruc- Halted
tion executed
while SSBY = 1
in SYSCR
Halted
Held
Halted Halted
and and
reset held^*1
Halted
and
reset
Held Held
• NMI
• IRQ₀ to IRQ₂
• RES
• STBY
Hardware Low input at
standby STBY pin
mode
Halted Halted Undeter
mined
Halted Halted
and and
reset reset
Halted
and
reset
Held^*2 High
• STBY
impedance • RES
Notes: 1. The refresh timer counter (RTCNT) and bits 7 and 6 of the refresh timer control/status register (RTMCSR) are
initialized. Other bits and registers hold their previous states.
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware
standby mode.
Legend
SYSCR: System control register
SSBY: Software standby bit
511