HD6413003TF10 Datasheet, PDF (186/717 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T₃ state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
performed. See figure 7-20.
RTCNT write cycle by CPU
T₁
T₂
T₃
ø
Address
Internal
write signal
Counter
clear signal
RTCNT
RTCNT address
N
H'00
Figure 7-20 Contention between RTCNT Write and Clear
166