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8.5 Interrupts
The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority.
Table 8-13 DMAC Interrupts
Group
0
1
Interrupt
DEND0A
DEND0B
DEND1A
DEND1B
DEND2A
DEND2B
DEND3A
DEND3B
Description
Short Address Mode
Full Address Mode
End of transfer on channel 0A End of transfer on
channel 0
End of transfer on channel 0B —
End of transfer on channel 1A End of transfer on
channel 1
End of transfer on channel 1B —
End of transfer on channel 2A End of transfer on
channel 2
End of transfer on channel 2B —
End of transfer on channel 3A End of transfer on
channel 3
End of transfer on channel 3B —
Interrupt Priority
High
Low
Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control
register (DTCR). Separate interrupt signals are sent to the interrupt controller.
The interrupt priority order among channels is channel 0 > channel 1 > channel 2 > channel 3, and
channel A > channel B. The interrupt priority order between groups can be modified in interrupt
priority register B (IPRB).
Figure 8-26 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and
DTIE = 1.
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