HYB18M512160BFX Datasheet, PDF (8/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Overview
1.3
Description
The HYB18M512160BFX is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
It is internally configured as a quad-bank DRAM.
The HYB18M512160BFX uses a double-data-rate architecture to achieve high-speed operation. The double-data-
rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit
wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock
cycle data transfers at the I/O pins.
The HYB18M512160BFX is especially designed for mobile applications. It operates from a 1.8V power supply.
Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can
further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-
Down (DPD) mode. For further power-savings the clock may be stopped during idle periods.
The HYB18M512160BFX is housed in a 60-ball P-VFBGA package. It is available in Commercial (0°C to 70°C)
temperature range.
CKE
CK
CK
CS
RAS
CAS
WE
Mode
Registers
Bank 3
Bank 2
Bank 1
A0-A12
BA0,BA1
15
13
13
2
2
10
Column Address
Counter / Latch
Bank 0
Memory Array
8192
(8192 x 512 x 32)
Sense Amplifier
IO Gating
DQM Mask Logic
Column
9
Decoder
Col0
CK/CK
Data
16
16
16
32
DQS
Generator
Input Reg.
Write Mask
FIFO
&
4
2
2
Drivers ₃₂
16
clk
out
clk
in
Data
2
CK/CK
Col0
Note 1: The Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent the actual
circuit implementation
Note 2: UDM / LDM are unidirectional signals (input only), but internally loaded to match the load of the bidirectional DQ and UDQS / LDQS
DQ0-
DQ15
UDM,
LDM
UDQS
LDQS
Figure 2 Functional Block Diagram
Data Sheet
8
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3