HYB18M512160BFX Datasheet, PDF (14/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
2.2.2 Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the
DQs. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 1) and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation. Address bits A0 - A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive
Strength, while bits A7 - A12 shall be written to zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register
BA1 BA0 A12 A11 A10 A9
1
0
0
0
0
0
(BA[1:0] = 10_B)
A8 A7 A6 A5
0
0
DS
A4 A3
(TCSR)
A2 A1 A0
PASR
Field Bits
DS [6:5]
TCSR [4:3]
PASR [2:0]
Type Description
w
Selectable Drive Strength
00 Full Drive Strength
01 Half Drive Strength
10 Quarter Drive Strength
Note: All other bit combinations are RESERVED.
w
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
w
Partial Array Self Refresh
000 all banks
001 half array (BA1 = 0)
010 quarter array (BA1 = BA0 = 0)
101 1/8 array (BA1 = BA0 = RA12 = 0)
110 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
Note: All other bit combinations are RESERVED.
2.2.2.1 Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may
be restricted to variable portions of the total array. The selection comprises all four banks (default), two banks, one
bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost
after a period defined by t_REF (cf. Table 14).
Data Sheet
14
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3