HYB18M512160BFX Datasheet, PDF (22/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
Table 11 Timing Parameters for READ Command
Parameter
Symbol
- 7.5
Unit Notes
DQ output access time from CK/CK
DQS output access time from CK/CK
DQ & DQS low-impedance time from CK/CK
DQ & DQS high-impedance time from CK/CK
DQS - DQ skew
DQ / DQS output hold time from DQS
Data hold skew factor
Read preamble
CL = 3
CL = 2
t_AC
t_DQSCK
t_LZ
t_HZ
t_DQSQ
t_QH
t_QHS
t_RPRE
Min.
2.0
2.0
1.0
–
–
t_HP-t_QHS
–
0.9
0.7
Max.
6.5
6.5
–
6.5
0.6
–
0.75
1.1
1.1
ns ¹⁾²⁾
ns ¹⁾²⁾
ns ³⁾
ns ³⁾
ns ⁴⁾
ns ⁵⁾
ns ⁵⁾
t_CK –
Read postamble
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
t_RPST
t_RAS
t_RC
t_RCD
t_RP
0.4
45
65
22.5
22.5
0.6
70,000
–
–
–
t_CK –
ns ⁶⁾
ns ⁶⁾
ns ⁶⁾
ns ⁶⁾
1) The output timing reference level is V_DDQ/2.
2) Parameters t_AC and t_QH are specified for full drive strength and a reference load of 20pF. This reference load is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. For half drive strength with a nominal load of 10pF parameters t_AC and t_QH are expected to be in the same
range. However, these parameters are not subject to production test but are estimated by device characterization. Use of
IBIS or other simulation tools for system validation is suggested.
3) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
4) t_DQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for
any given cycle.
5) t_QH = t_HP - t_QHS, where t_HP = minimum half clock period for any given cycle and is defined by clock high or clock low (t_CL,
t_CH). t_QHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on
one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin
skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period ; round to the next higher integer.
During READ bursts, the valid data-out element from the starting column address will be available following the
CAS latency after the READ command.
The diagrams in Figure 13 show general timing for each supported CAS latency setting. DQS is driven by the DDR
Mobile-RAM along with output data. The initial low state on DQS is known as the read preamble; the low state
coincident with the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
Data Sheet
22
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3