HYB18M512160BFX Datasheet, PDF (17/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
2.4
Commands
Table 6 Command Overview
Command
NOP DESELECT
NO OPERATION
ACT ACTIVE (Select bank and row)
RD READ (Select bank and column and start read burst)
WR WRITE (Select bank and column and start write burst)
BST BURST TERMINATE or DEEP POWER-DOWN
PRE PRECHARGE (Deactivate row in bank or banks)
ARF AUTO REFRESH or SELF REFRESH entry
MRS MODE REGISTER SET
CS RAS CAS WE Address Notes
HXXX
X
1)2)
L HHH
X
1)2)
L
L
H
H Bank / Row ¹⁾³⁾
L H L H Bank / Col ¹⁾⁴⁾
L
H
L
L Bank / Col ¹⁾⁴⁾
L HH L
X
1)5)
L LHL
Code ¹⁾⁶⁾
L L LH
X
1)7)8)
L
L
L
L Op-Code ¹⁾⁹⁾
1) CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN.
2) DESELECT and NOP are functionally interchangeable.
3) BA0, BA1 provide the bank address, and A0 - A12 provide the row address.
4) BA0, BA1 provide the bank address, A0 - A9 provide the column address; A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
5) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER-DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ bursts with Auto Precharge disabled only; it is undefined (and should not be used) for read
bursts with Auto Precharge enabled, and for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
Table 7 DM Operation
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data provided coincident with the corresponding data
DM DQs Notes
L Valid ¹⁾
H
X ¹⁾
Address (BA0, BA1, A0 - A12) and command inputs (CKE, CS, RAS, CAS, WE) are all registered on the crossing
of the positive edge of CK and the negative edge of CK. Figure 5 shows the basic timing parameters, which apply
to all commands and operations.
CK
CK
Input
t_CK
t_CH
t_CL
Valid
t_IS t_IH
Valid
Valid
Figure 5 Address / Command Inputs Timing Parameters
= Don't Care
Data Sheet
17
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3