HYB18M512160BFX Datasheet, PDF (49/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.3
Operating Currents
Table 26 Maximum Operating Currents^1)2)3)4)5)
Parameter & Test Conditions
Symbol Value Unit
- 7.5
Operating one bank active-precharge current:
I_DD0
t_RC = t_RCmin; t_CK = t_CKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are
SWITCHING; data bus inputs are STABLE
50 mA
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, t_CK = t_CKmin; address and control inputs are SWITCHING;
data bus inputs are STABLE
I_DD2P
2.2 mA
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD2PS
2.1 mA
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, t_CK = t_CKmin; address and control inputs are SWITCHING;
data bus inputs are STABLE
I_DD2N
15 mA
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD2NS
2.6 mA
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD3P
2.3 mA
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
I_DD3PS
2.2 mA
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD3N
22 mA
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
I_DD3NS
2.7 mA
Operating burst read current:
one bank active; BL = 4; CL = 3; t_CK = t_CKmin; continuous read bursts;
I_OUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current:
one bank active; BL = 4; t_CK = t_CKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
I_DD4R
75 mA
I_DD4W
75 mA
Auto-Refresh current:
I_DD5
t_RC = t_RFCmin; t_CK = t_CKmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING;
data bus inputs are STABLE
135 mA
Self refresh current:
I_DD6
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus inputs
2 mA
are STABLE
Deep Power Down current
1) 0 °C ≤ T_C ≤ 70 °C (comm.); V_DD = V_DDQ = 1.70 V - 1.90 V.
Recommended Operating Conditions unless otherwise noted
I_DD8
50⁶⁾ µA
2) IDD specifications are tested after the device is properly intialized and measured at 133 MHz for -7.5 speed grade.
3) Input slew rate is 1.0 V/ns.
Data Sheet
49
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3