HYB18M512160BFX Datasheet, PDF (21/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
2.4.5 READ
CK
CK
CKE
CS
RAS
CAS
WE
A0-A9
A10
BA0,BA1
(High)
CA
Enable AP
AP
Disable AP
BA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
Figure 11 READ Command
READ bursts are initiated with a READ command, as
shown in Figure 11.
Basic timings for the DQs are shown in Figure 12; they
apply to all read operations.
The starting column and bank addresses are provided
with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto
Precharge is enabled, the row that is accessed will start
precharge at the completion of the burst, provided t_RAS
has been satisfied. For the generic READ commands
used in the following illustrations, Auto Precharge is
disabled.
CK
CK
DQS
t_CK
tACmax
DQ
t_CK
t_CH
t_CL
t_RPRE
t_DQSCK
t_AC
t_LZ
t_DQSCK
t_RPST
t_DQSQmax
t_HZ
DO n
t_QH
DO n+1 DO n+2 DO n+3
t_QH
DQS
tACmin
t_RPRE
t_DQSCK
t_DQSCK
t_RPST
t_AC
t_DQSQmax
t_HZ
DQ
t_LZ
DO n
t_QH
DO n+1 DO n+2 DO n+3
t_QH
DO n = Data Out from column n
Burst Length = 4 in the case shown
= Don't Care
CAS Latency = 3 in the case shown
All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC
Figure 12 Basic READ Timing Parameters for DQs
Data Sheet
21
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3