HYB18M512160BFX Datasheet, PDF (47/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Electrical Characteristics
Table 23 AC Characteristics^1)2)3)4) (cont’d)
Parameter
Symbol
- 7.5
Unit Notes
Min. Max.
Internal write to Read command delay
t_WTR
1
–
t_CK –
Self refresh exit to next valid command delay
t_XSR
120
–
ns ²²⁾
Exit power down delay
t_XP
t_CK+ t_IS
–
ns
CKE minimum high or low time
t_CKE
2
–
t_CK –
Refresh period
t_REF
–
64 ms –
Average periodic refresh interval (8192 rows)
t_REFI
–
7.8
µs ²⁴⁾
1) 0 °C ≤ T_C ≤ 70 °C (comm.); V_DD = V_DDQ = 1.70 V - 1.90 V. All voltages referenced to V_SS.
2) All parameters assume proper device initialization.
3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference
level for signals other than CK/CK is V_DDQ/2.
4) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
5) The output timing reference level is V_DDQ/2.
6) Parameters t_ac and t_DQSCK are specified for full drive strength and a reference load as shown below. This circuit is not
intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented
by a production tester. For half drive strength with a nominal load of 10pF parameters t_AC and t_DQSCK are expected to be in
the same range. However, these parameters are not subject to production test but are estimated by device characterization.
Use of IBIS or other simulation tools for system validation is suggested.
I/O
Z₀ = 50 Ohms
20 pF
7) Min (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for t_CL and t_CH).
8) t_QH = t_HP - t_QHS, where t_HP = minimum half clock period for any given cycle and is defined by clock high or clock low (t_CL,
t_CH). t_QHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on
one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin
skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
9) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
10) DQ, DM and DQS input slew rate is measured between V_ILD(DC) and V_IHD(AC) (rising) or V_IHD(DC) and V_ILD(AC) (falling).
11) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
12) Input slew rate ≥ 1.0 V/ns..
13) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
14) These parameters guarantee device timing. They are verified by device characterization but are not subject to production
test.
15) The transition time for address and command inputs is measured between V_IH and V_IL.
16) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
17) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
18) t_DQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for
any given cycle.
19) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
20) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
Data Sheet
47
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3