HYB18M512160BFX Datasheet, PDF (20/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

2.4.4 ACTIVE
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
(High)
RA
BA
= Don't Care
BA = Bank Address
RA = Row Address
Figure 9 ACTIVE Command
HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
Before any READ or WRITE commands can be issued
to a bank within the DDR Mobile-RAM, a row in that
bank must be “opened” (activated). This is
accomplished via the ACTIVE command and
addresses BA0, BA1, A0 - A12 (see Figure 9), which
decode and select both the bank and the row to be
activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be
issued to that row, subject to the t_RCD specification. A
subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by t_RC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by t_RRD.
CK
CK
Command
A0-A12
BA0, BA1
ACT
Row
BA x
NOP
t_RRD
Figure 10 Bank Activate Timings
ACT
Row
BA y
NOP
NOP
t_RCD
RD/WR
Col
BA y
NOP
= Don't Care
Table 10 Timing Parameters for ACTIVE Command
Parameter
Symbol
- 7.5 Unit Notes
Min. Max.
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
t_RC
65
–
ns ¹⁾
t_RCD 22.5
–
ns ¹⁾
t_RRD
15
–
ns ¹⁾
1) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period ; round to the next higher integer.
Data Sheet
20
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3