HYB18M512160BFX Datasheet, PDF (28/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
2.4.7
WRITE
CK
CK
CKE
CS
RAS
CAS
WE
A0-A9
A10
BA0,BA1
(High)
CA
Enable AP
AP
Disable AP
BA
= Don't Care
WRITE bursts are initiated with a WRITE command, as
shown in Figure 21. Basic timings for the DQs are
shown in Figure 22; they apply to all write operations.
The starting column and bank addresses are provided
with the WRITE command, and Auto Precharge is
either enabled or disabled for that access. If Auto
Precharge is enabled, the row being accessed is
precharged at the completion of the write burst. For the
generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
Figure 21
BA = Bank Address
CA = Column Address
AP = Auto Precharge
WRITE Command
CK
CK
Case 1:
tDQSS = min
DQS
DQ, DM
t_CK
t_CH
t_CL
t_DQSS
t_DQSH
t_DSH
t_WPRES
t_WPRE
t_DS
DI n
t_DQSL
t_DH
t_DSH
t_WPST
Case 2:
tDQSS = max
DQS
t_WPRES
DQ, DM
t_DQSS
t_DQSH
t_DSS
t_WPRE
t_DS
DI n
t_DQSL
t_DH
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order following DI n.
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS
must fall within the ± 25% window of the corresponding positive clock edge.
Figure 22 Basic WRITE Timing Parameters for DQs
Data Sheet
28
t_DSS
t_WPST
= Don't Care
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3