HYB18M512160BFX Datasheet, PDF (30/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
DQS
DQ
DM
WRITE
BA,Col b
t_DQSSmin
NOP
Di b
t_DQSSmax
Di b
NOP
NOP
NOP
NOP
DI b = Data In to column b.
3 subsequent elements of Data In are applied in the programmed order following DI b.
A non-interrupted burst of 4 is shown.
A10 is LOW with the WRITE command (Auto Precharge is disabled)
= Don't Care
Figure 23 WRITE Burst (min. and max. tDQSS)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any clock
cycle following the previous WRITE command. The first data element from the new burst is applied after either the
last element of a completed burst or the last desired data element of a longer burst which is being truncated. The
new WRITE command should be issued x clock cycles after the first WRITE command, where x equals the number
of desired data element pairs (pairs are required by the 2n prefetch architecture).
Figure 24 shows concatenated WRITE bursts of 4.
Data Sheet
30
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3