HYB18M512160BFX Datasheet, PDF (12/52 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM

HYB18M512160BFX
512-Mbit DDR Mobile-RAM
Functional Description
2.2.1.1 Burst Length
READ and WRITE accesses to the DDR Mobile-RAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be accessed for
a given READ or WRITE command. Burst lengths of 2, 4, 8 or 16 locations are available.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary
is reached. The block is uniquely selected by A1 - A9 when the burst length is set to two, by A2 - A9 when the
burst length is set to four, by A3 - A9 when the burst length is set to eight and by A4 - A9 when the burst length
is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both READ and WRITE bursts.
2.2.1.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
2.2.1.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 * t_CK + t_AC).
If a READ command is registered and the latency is 2 clocks, the first data element will be valid after (t_CK + t_AC).
For details please refer to the READ command description.
Data Sheet
12
Rev. 1.10, 2006-11
04052006-4SYQ-ZRN3