HYB18T512400BF Datasheet, PDF (7/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and
Buffer Type columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 6 Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin Buffer
Type Type
Function
Clock Signals ×4/×8 organizations
E8
CK
I
SSTL Clock Signal CK, Complementary Clock Signal CK
F8
CK
I
SSTL
F2
CKE
I
SSTL Clock Enable
Clock Signals ×16 organization
J8
CK
I
SSTL Clock Signal CK, Complementary Clock Signal CK
K8
CK
I
SSTL Note: See functional description in x4/x8 organization
K2
CKE
I
SSTL Clock Enable
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL Row Address Strobe (RAS), Column Address Strobe (CAS),
G7
CAS
I
SSTL ^{Write Enable (WE)}
F3
WE
I
SSTL
G8
CS
I
SSTL Chip Select
Control Signals ×16 organization
K7
RAS
I
SSTL Row Address Strobe (RAS), Column Address Strobe (CAS),
L7
CAS
I
SSTL ^{Write Enable (WE)}
K3
WE
I
SSTL
L8
CS
I
SSTL Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL Bank Address Bus 1:0
G3
BA1
I
SSTL
Internet Data Sheet
7
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z