HYB18T512400BF Datasheet, PDF(14/57 Page) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512400BF Datasheet, PDF (14/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512xxxBFâ[2.5â¦5]

512-Mbit Double-Data-Rate-Two SDRAM

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Pin Configuration for Ã16 components, PG-TFBGA-84-8

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Notes

1. UDQS/UDQS is data strobe for DQ[15:8],

LDQS/LDQS is data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the

data mask signal for DQ[15:8]

3. VDDL and VSSDL are power and ground for the DLL.

VDDL is connected to VDD on the device. VDD, VDDQ,

VSSDL, VSS, and VSSQ are isolated on the device.

Internet Data Sheet

14

Rev. 1.05, 2007-01

03292006-YBYM-WG0Z

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