HYB18T512400BF Datasheet, PDF (19/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Table 12 EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010_B)
Field Bits Type¹⁾ Description
BA2 16
w
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
BA [15:14] w
A
[13:8] w
0_B BA2, Bank Address
Bank Adress[15:14]
00_B BA, MRS
01_B BA, EMRS(1)
10_B BA, EMRS(2)
11_B BA, EMRS(3): Reserved
Address Bus[13:8]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0_B A[13:8], Address bits
A
7
w
Address Bus[7], adapted self refresh rate for TCase > 85°C
0_B A7, disable
1_B A7, enable ²⁾
A
[6:4] w
Address Bus[6:4]
0_B A[6:4], Address bits
A
3
w
Address Bus[3], Duty Cycle Correction (DCC)
0_B A[3], DCC disabled
1_B A[3], DCC enabled
Partial Self Refresh for 4 banks
A
[2:0] w
Address Bus[2:0], Partial Array Self Refresh for 4 Banks³⁾
000_B PASR0, Full Array
001_B PASR1, Half Array (BA[1:0]=00, 01)
010_B PASR2, Quarter Array (BA[1:0]=00)
011_B PASR3, Not defined
100_B PASR4, 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5, Half array (BA[1:0]=10, 11)
110_B PASR6, Quarter array (BA[1:0]=11)
111_B PASR7, Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1"
before the self refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost
if self refresh is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
Internet Data Sheet
19
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z