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HYB18T512400BF Datasheet, PDF (42/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM
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HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 42 Timing Parameter by Speed Grade - DDR2–667 (cont’d)
Parameter
Symbol
DDR2–667
Min.
Max.
DQS-DQ skew (for DQS & associated DQ tDQSQ
—
240
signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
DQ and DM input setup time (differential data tDS(base) 100
—
strobe)
DQ and DM input setup time (single ended tDS1(base) ––
—
data strobe)
DQS falling edge hold time from CK (write tDSH
0.2
—
cycle)
DQS falling edge to CK setup time (write tDSS
0.2
—
cycle)
Clock half period
tHP
Data-out high-impedance time from CK / CK tHZ
Address and control input hold time
tIH(base)
Address and control input pulse width
tIPW
(each input)
MIN. (tCL, tCH)
—
tAC.MAX
275
—
0.6
—
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
200
2 × tAC.MIN
tAC.MIN
2
0
tHPQ – tQHS
—
—
—
—
tAC.MAX
tAC.MAX
—
12
—
340
7.8
3.9
Auto-Refresh to Active/Auto-Refresh
tRFC
105
—
command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
tRP
tRPRE
tRPST
tRRD
tRP
0.9
0.40
7.5
10
—
1.1
0.60
—
—
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
tRTP
tWPRE
tWPST
tWR
7.5
0.35 x tCK
0.40
15
—
—
0.60
—
Write recovery time for write with Auto-
WR
Precharge
tWR/tCK
—
Internal Write to Read command delay
tWTR
7.5
—
Unit
ps
Note1)2)3)4)5)
6)
9)
tCK
—
ps —
ps —
tCK
—
tCK
—
—
10)
ps
11)
ps —
tCK
—
ps —
ps —
ps —
tCK
—
ns —
——
ps —
µs
12)13)
µs
14)
ns
15)
ns
16)
tCK
—
tCK
—
ns
17)
ns —
ns —
tCK
—
tCK
18)
ns —
tCK
19)
ns
20)
Internet Data Sheet
42
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
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