HYB18T512400BF Datasheet, PDF (26/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
Table 21 Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Unit Note
Min.
Typ.
Max.
V_DD
Supply Voltage
1.7
1.8
1.9
V
1)
V_DDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
—
V_DDQ
V_REF
V_TT
Supply Voltage for Output 1.7
1.8
1.9
V
—
Input Reference Voltage
0.49 × V_DDQ 0.5 × V_DDQ
0.51 × V_DDQ
V
2)3)
Termination Voltage
V_REF – 0.04 V_REF
V_REF + 0.04
V
4)
1) V_DDQ tracks with V_DD, V_DDDL tracks with V_DD. AC parameters are measured with V_DD, V_DDQ and V_DDDL tied together.
2) The value of V_REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V_REF
is expected to be about 0.5 × V_DDQ of the transmitting device and V_REF is expected to track variations in V_DDQ.
3) Peak to peak ac noise on V_REF may not exceed ± 2% V_REF (dc)
4) V_TT is not applied directly to the device. V_TT is a system supply for signal termination resistors, is expected to be set equal
to V_REF, and must track variations in die dc level of V_REF.
Table 22 ODT DC Electrical Characteristics
Parameter / Condition
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Symbol
Rtt1(eff)
Min.
60
Nom. Max.
75
90
Unit
Ω
Note
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff) 120 150 180
Ω
—
Termination resistor impedance value for
Rtt3(eff) 40
50
60
Ω
—
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Deviation of V_M with respect to V_DDQ / 2
delta V_M –6.00 —
+ 6.00 %
2)
1) Measurement Definition for Rtt(eff): Apply V_IH(ac) and V_IL(ac) to test pin separately, then measure current I(V_IHac) and I(V_ILac)
respectively. Rtt(eff) = (V_IH(ac) – V_IL(ac)) /(I(V_IHac) – I(V_ILac)).
2) Measurement Definition for V_M: Turn ODT on and measure voltage (V_M) at test pin (midpoint) with no load:
delta V_M = ((2 x V_M / V_DDQ) – 1) x 100%
Table 23 Input and Output Leakage Currents
Symbol Parameter / Condition
Min. Max.
I_IL
Input Leakage Current; any input 0 V < V_IN < V_DD
–2
+2
I_OL
Output Leakage Current; 0 V < VOUT < V_DDQ
–5
+5
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Unit
µA
µA
Note
1)
2)
Internet Data Sheet
26
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z