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HYB18T512400BF Datasheet, PDF (47/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM
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HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 44 Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Min.
DQ output access time from CK / CK
tAC
CAS A to CAS B command period
tCCD
CK, CK high-level width
tCH
CKE minimum high and low pulse width tCKE
CK, CK low-level width
tCL
Auto-Precharge write recovery +
tDAL
precharge time
–600
2
0.45
3
0.45
WR + tRP
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH
DQ and DM input hold time (differential tDH(base)
275
data strobe)
DQ and DM input hold time (single ended tDH1(base) –25
data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write
cycle)
tDIPW
tDQSCK
tDQSL,H
0.35
–500
0.35
DQS-DQ skew (for DQS & associated DQ tDQSQ
—
signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
DQ and DM input setup time (differential tDS(base)
150
data strobe)
DQ and DM input setup time (single ended tDS1(base) –25
data strobe)
DQS falling edge hold time from CK (write tDSH
0.2
cycle)
DQS falling edge to CK setup time (write tDSS
0.2
cycle)
Clock half period
tHP
Data-out high-impedance time from CK / tHZ
CK
MIN. (tCL, tCH)
—
Address and control input hold time
tIH(base)
475
Address and control input pulse width
tIPW
0.6
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
350
2×
tAC.MIN
tAC.MIN
2
0
tHP –tQHS
Internet Data Sheet
47
Max.
+600
—
0.55
—
0.55
—
––
––
—
—
+500
—
350
+ 0.25
—
—
—
—
tAC.MAX
—
—
—
tAC.MAX
tAC.MAX
—
12
—
Unit Note1)2)3)4)5)
6)
ps —
tCK
—
tCK
—
tCK
—
tCK
—
tCK
7)
ns
8)
ps —
ps —
tCK
—
ps —
tCK
—
ps
9)
tCK
—
ps —
ps —
tCK
—
tCK
—
10)
ps
11)
ps —
tCK
—
ps —
ps —
ps —
tCK
—
ns —
——
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
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