HYB18T512400BF Datasheet, PDF(17/57 Page) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512400BF Datasheet, PDF (17/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512xxxBFâ[2.5â¦5]

512-Mbit Double-Data-Rate-Two SDRAM

Table 10 Mode Register Definition (BA[2:0] = 000B)

Field Bits Type1)

Description

BT

3

w

BL

[2:0] w

Burst Type

0B BT, Sequential

1B BT, Interleaved

Burst Length

Note: All other bit combinations are illegal.

010B BL, 4

011B BL, 8

1) w = write only register bits

2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by

tCK (in ns) and rounding up to the next integer: WR [cycles] â¥ tWR (ns) / tCK (ns). The mode register must be programmed to

fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by

tCK.MIN.

"! "! "! ! ! ! ! ! ! ! ! ! ! ! ! ! !

1OFF 2$ 1 3 $1 3 /#$ 0ROGRAM

2TT

!,

2TT $)# $, ,

REG A DDR

W W

W

W

W

W W W

-0"4

Table 11 Extended Mode Register Definition (BA[2:0] = 001B)

Field Bits Type1)

Description

BA2

16 reg. addr. Bank Address [2]

Note: BA2 not available on 256 Mbit and 512 Mbit components

BA1

15

BA0

14

0B BA2, Bank Address

Bank Address [1]

0B BA1, Bank Address

Bank Address [0]

0B BA0, Bank Address

Internet Data Sheet

17

Rev. 1.05, 2007-01

03292006-YBYM-WG0Z

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