HYB18T512400BF Datasheet, PDF (38/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 40 Speed Grade Definition Speed Bins for DDR2–400B
Speed Grade
DDR2–400
Unit Note
IFX Sort Name
–5
CAS-RCD-RP latencies
3–3–3
t_CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
t_CK
5
8
ns
1)2)3)4)
@ CL = 4
t_CK
5
8
ns
—
Row Active Time
@ CL = 5
t_CK
t_RAS
5
8
ns
—
40
70000
ns
5)
Row Cycle Time
t_RC
55
—
ns
—
RAS-CAS-Delay
t_RCD
15
—
ns
—
Row Precharge Time
t_RP
15
—
ns
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as low.
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x t_REFI.
Internet Data Sheet
38
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z