HYB18T512400BF Datasheet, PDF (24/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 17 Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State¹⁾ CKE
Previous Cycle⁶⁾ Current Cycle
(N-1)
(N)
Command (N)²⁾³⁾ Action (N)
RAS, CAS, WE, CS
Note⁴⁾⁵⁾
Power-Down L
L
Self Refresh L
L
X
Maintain Power-Down ⁷⁾⁸⁾
H
DESELECT or NOP Power-Down Exit
9)10)11)
L
X
Maintain Self Refresh ¹²⁾
L
Bank(s)
H
Active
H
DESELECT or NOP Self Refresh Exit
13)14)
L
DESELECT or NOP Active Power-Down Entry ¹⁵⁾
All Banks Idle H
L
DESELECT or NOP Precharge Power-Down —
Entry
H
Any State other H
than
listed above
L
AUTOREFRESH Self Refresh Entry
16)
H
Refer to the Command Truth Table
17)
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements
8) “X” means “don’t care (including floating around V_REF)” in Self Refresh and Power Down. However ODT must be driven
HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) t_CKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of t_IS + 2×t_CKE + t_IH.
12) V_REF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after t_XSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Table 18 Data Mask (DM) Truth Table
Name (Function)
DM
Write Enable
L
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
DQs
Valid
X
Note
1)
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Internet Data Sheet
24
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z