HYB18T512400BF Datasheet, PDF (41/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for t_CL and t_CH).
11) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ T_CASE ≤ 85 °C
14) 85 °C < T_CASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) t_RP(A) for a Precharge-All command for an 8 bank device is equal to t_RP + 1t_CK, where t_RP are the values for a single bank
precharge.
17) The t_RRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the t_WPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the t_WR timing parameter, where
WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded up to the next integer value. t_DAL = WR + (t_RP/t_CK). For each of the terms, if not
already an integer, round to the next highest integer. t_CK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum t_WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing t_XARDS has to be satisfied.
Table 42 Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Min.
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge t_DAL
time
–450
2
0.45
3
0.45
WR + t_RP
Minimum time clocks remain ON after CKE t_DELAY
asynchronously drops LOW
t_IS + t_CK + t_IH
DQ and DM input hold time (differential data t_DH(base) 175
strobe)
DQ and DM input hold time (single ended t_DH1(base) ––
data strobe)
DQ and DM input pulse width (each input) t_DIPW
DQS output access time from CK / CK
t_DQSCK
DQS input low (high) pulse width (write cycle) t_DQSL,H
0.35
–400
0.35
Max.
+450
—
0.55
—
0.55
—
—
––
—
—
+400
—
Unit
ps
t_CK
t_CK
t_CK
t_CK
t_CK
Note^1)2)3)4)5)
6)
—
—
—
—
—
7)
ns
8)
ps —
ps —
t_CK
—
ps —
t_CK
—
Internet Data Sheet
41
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z