HYB18T512400BF Datasheet, PDF (45/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 43 Timing Parameter by Speed Grade - DDR2-533 (cont’d)
Parameter
Symbol
DDR2–533
Min.
Max.
Unit
Note^1)2)3)4)
5)6)
Data hold skew factor
Average periodic refresh Interval
t_QHS
—
t_REFI
—
—
400
ps —
7.8
µs
12)13)
3.9
µs
14)
Auto-Refresh to Active/Auto-Refresh
t_RFC
105
—
ns
15)
command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
t_RP
t_RPRE
t_RPST
t_RRD
t_RP
0.9
0.40
7.5
10
—
1.1
0.60
—
—
ns
16)
t_CK
—
t_CK
—
ns
17)
ns —
Internal Read to Precharge command
t_RTP
7.5
delay
—
ns —
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
t_WPRE
t_WPST
t_WR
0.25 x t_CK
0.40
15
—
0.60
—
t_CK
—
t_CK
18)
ns —
Write recovery time for write with Auto- WR
Precharge
t_WR/t_CK
—
t_CK
19)
Internal Write to Read command delay t_WTR
7.5
Exit power down to any valid command t_XARD
2
(other than NOP or Deselect)
—
ns
20)
—
t_CK
21)
Exit active power-down mode to Read
t_XARDS
6 – AL
—
command (slow exit, lower power)
t_CK
—
Exit precharge power-down to any valid t_XP
2
command (other than NOP or Deselect)
—
t_CK
—
Exit Self-Refresh to non-Read command t_XSNR
t_RFC +10
—
ns —
Exit Self-Refresh to Read command
t_XSRD
200
—
t_CK
—
1) V_DDQ = 1.8V ± 0.1V; V_DD = 1.8V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is
recognized as low.
6) The output timing reference voltage level is V_TT.
7) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for t_CL and t_CH).
Internet Data Sheet
45
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z