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HYB18T512400BF Datasheet, PDF (39/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7.2
AC Timing Parameters
List of Timing Parameters Tables.
• Table 41 “Timing Parameter by Speed Grade - DDR2–800” on Page 39
• Table 42 “Timing Parameter by Speed Grade - DDR2–667” on Page 41
• Table 43 “Timing Parameter by Speed Grade - DDR2-533” on Page 44
• Table 44 “Timing Parameter by Speed Grade - DDR2-400” on Page 47
Table 41 Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Min.
Max.
DQ output access time from CK / CK
tAC
CAS A to CAS B command period
tCCD
CK, CK high-level width
tCH
CKE minimum high and low pulse width tCKE
CK, CK low-level width
tCL
Auto-Precharge write recovery + precharge tDAL
time
–400
2
0.45
3
0.45
WR + tRP
+400
—
0.55
—
0.55
—
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH ––
DQ and DM input hold time (differential tDH(base)
125
––
data strobe)
DQ and DM input hold time (single ended tDH1(base)
––
—
data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write
cycle)
tDIPW
tDQSCK
tDQSL,H
0.35
–350
0.35
—
+350
—
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
—
200
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
DQ and DM input setup time (differential tDS(base)
50
—
data strobe)
DQ and DM input setup time (single ended tDS1(base)
––
—
data strobe)
DQS falling edge hold time from CK (write tDSH
cycle)
0.2
—
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
—
Clock half period
tHP
Data-out high-impedance time from CK / tHZ
CK
MIN. (tCL, tCH)
—
tAC.MAX
Address and control input hold time
tIH(base)
250
—
Address and control input pulse width
tIPW
(each input)
0.6
—
Unit Note1)2)3)4)5)
6)
ps —
tCK
—
tCK
—
tCK
—
tCK
—
tCK
7)
ns
8)
ps —
ps —
tCK
—
ps —
tCK
—
ps
9)
tCK
—
ps —
ps —
tCK
—
tCK
—
—
10)
ps
11)
ps —
tCK
—
Internet Data Sheet
39
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z