HYB18T512400BF Datasheet, PDF (28/57 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Figure 4 Single-ended AC Input Test Conditions Diagram
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Table 27 Differential DC and AC Input and Output Logic Levels
Symbol
V_IN(dc)
V_ID(dc)
V_ID(ac)
V_IX(ac)
V_OX(ac)
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross point input
voltage
AC differential cross point output
voltage
Min.
–0.3
0.25
0.5
0.5 × V_DDQ – 0.175
0.5 × V_DDQ – 0.125
Max.
V_DDQ + 0.3
V_DDQ + 0.6
V_DDQ + 0.6
0.5 × V_DDQ + 0.175
0.5 × V_DDQ + 0.125
Unit
—
—
V
V
V
Note
1)
2)
3)
4)
5)
1) V_IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) V_ID(dc) specifies the input differential voltage V_TR– V_CP required for switching. The minimum value is equal to V_IH(dc) – V_IL(dc).
3) V_ID(ac) specifies the input differential voltage V_TR – V_CP required for switching. The minimum value is equal to V_IH(ac) – V_IL(ac).
4) The value of V_IX(ac) is expected to equal 0.5 × V_DDQ of the transmitting device and V_IX(ac) is expected to track variations in
V_DDQ. V_IX(ac) indicates the voltage at which differential input signals must cross.
5) The value of V_OX(ac) is expected to equal 0.5 × V_DDQ of the transmitting device and V_OX(ac) is expected to track variations in
V_DDQ. V_OX(ac) indicates the voltage at which differential input signals must cross.
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Figure 5 Differential DC and AC Input and Output Logic Levels Diagram
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Internet Data Sheet
28
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z