SLRC400 Datasheet, PDF (81/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
11 START UP PHASE
The phases executed during the start up are shown in the following figure:
Start Up Phase
t_PD
t_Reset
States
Hard Power
Down Phase
Reset Phase
Figure 11-1: Start Up Procedure
t_Init
Initialising
Phase
Ready
11.1 Hard Power Down Phase
The Hard Power Down Phase is active during the following cases:
• Power On Reset caused by power up at pin DVDD
(active while DVDD is below the digital reset threshold)
• Power On Reset caused by power up at pin AVDD
(active while AVDD is below the analog reset threshold)
• A HIGH level on pin RSTPD
(active while pin RSTPD is HIGH)
11.2 Reset Phase
The Reset Phase follows the Hard Power Down Phase automatically. It takes 512 clocks. During the Reset
Phase, some of the register bits are preset by hardware. The respective reset values are given in the
description of each register (see 5.2.).
Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and that it will
take a certain time t_osc until the oscillator is stable.
11.3 Initialising Phase
The Initialising Phase follows the Reset Phase automatically. It takes 128 clocks. During the Initialising
Phase the content of the E²PROM blocks 1 and 2 is copied into the registers 10_hex to 2F_hex (see 6.3.).
Note: At production test, the SL RC400 is initialised with default configuration values. This reduces the
µ-Processors effort for configuring the device to a minimum.
81
Preliminary